Memory

Display status of the system memory.

Display Total Usable Memory Capacity.

Memory speed is changed dynamically according to the combination of the installed processor SKU, DIMM type, number of DIMMs per channel, and system board support.

The system operates at the rated speed of the slowest DIMM in the system when populated with different speed DIMMs. If DIMMs are installed with a rated speed below 4000, this will cause the memory speed set to the minimum value.

Enable or disable low-power features for DIMMs.

Specify the number of desired NUMA nodes per processor socket (e.g. NPS1 means 1 NUMA per socket).

NPS0 will attempt to interleave the 2 processor sockets together (non-NUMA mode).

Set the period of time between successive DRAM scrub events.

Enable or disable DRAM Post Package Repair.

[Disabled]: Disable memory self-healing feature.

[PMU Mem BIST]: Use vendor-provided physical layer management unit firmware (PMU) to test memory on all channels simultaneously. Failing memory will be repaired using soft (temporary) or hard (permanent) repair, depending on the post package repair (PPR) configuration.

[Self-Healing Mem BIST]: Use JEDEC DRAM built-in self-test (BIST) to detect failure and attempt a hard repair (permanent) for the failing memory row.

[PMU and Self-Healing Mem BIST]: Run PMU Mem BIST and then Self-Healing Mem BIST tests sequentially.

Control secure memory encryption enable.

Enable or disable memory interleaving.

Value of NUMA nodes per socket will be honored regardless of this setting.

Specify the stored refresh limit to required enter sub-urgent refresh mode.

Constraint: SubUrgRefLowerBound is less than or equal to UrgRefLimit.

Valid value: 6 ~ 1.

Specify the stored refresh limit to required enter urgent refresh mode.

Constraint: SubUrgRefLowerBound is less than or equal to UrgRefLimit.

Valid value: 6 ~ 1.

For better performance, a refresh rate of 1x is recommended.

To mitigate the rowhammer issue, choosing refresh rate 2x may affect the performance.

TSME stands for Transparent Secure Memory Encryption.

SME-MK encryption mode.

SEV VMs using ASIDs below the SEV-ES ASID Space Limit must enable the SEV-ES feature.

ASIDs from SEV-ES ASID Space Limit to (SEV ASID Count + 1) can only be used with SEV VMs.

If this field is set to (SEV ASID Count + 1), all ASIDs are forced to be SEV-ES ASIDs. Hence, the valid values for this field is 1 - (SEV ASID Count + 1)

Can be used to disable SEV. To re-enable SEV, a POWER CYCLE is needed after selecting the 'Enabled' option.

Attempt to remap DRAM out of the space just below the 1TB boundary. The ability to remap depends on DRAM configuration, NPS, and interleaving selection, and may not always be possible.