Processors

When [Performance] is selected, performance is more predictable (deterministic) and operates at the lowest common denominator among the cores. But aggregate peak performance may be reduced.

When [Power] is selected, cores can scale frequency independently. Aggregate performance may be higher, but predictability is lower.

When [Enabled] is selected, cores can run at turbo frequencies.

Set the maximum power consumption for the processor.

[Auto] sets cTDP=TDP for the installed processor SKU.

[Maximum] sets the maximum allowed cTDP value for the installed processor SKU. Usually, maximum is greater than TDP. If a manual value is entered that is greater than the maximum value allowed, the value will be internally limited to the maximum allowable value. cTDP is only configurable before booting the operating system.

Set the power consumption for the processor.

Set the CPU package power limit.

If [Auto] is selected, it will be set to the maximum value allowed by the installed processor.

If a manual value is entered that is greater than the maximum value allowed, the value will be internally limited to the maximum allowable value.

The maximum value allowed for PPL is the cTDP limit. Compared to cTDP, Package Power Limit (PPL) can be changed at runtime and PPL supports a much lower effective limit than cTDP.

Package Power Limit (PPT) [W].

Sets the xGMI speed.

N is the maximum speed and is auto-calculated from the system board capabilities. For system boards that do not support 4 discrete xGMI speed choices, some menu choices besides “Minimum” will result in the xGMI speed getting set to the minimum value.

Sets the xGMI speed.

N is the maximum speed and is auto-calculated from the system board capabilities. NUMA-unaware workloads may need maximum xGMI bandwidth because of extensive cross socket communications. NUMA-aware workloads may want to minimize xGMI power because they do not have a lot of cross socket traffic and prefer to use the increased CPU boost.

Enable or disable IO based C-state generation and DF C-states.

When [Auto] is selected, the processor DF P-states (uncore P-states) are dynamically adjusted. The frequency dynamically changes based on the workload.

Selecting P0, P1, P2, P3 or P4 forces the DF to a specific P-state frequency.

Enable or disable data fabric (DF) C-states.

Data fabric C-states may be entered when all cores are in CC6.

Enable or disable processor P1 P-state.

Enable or disable processor P2 P-state.

If [Enabled] is selected, each CCX in the system will be declared as a separate NUMA domain.

If [Disabled] is selected, memory addressing/NUMA nodes per socket will be declared.

Enable or disable L1 stream HW prefetcher.

Fetch the next cache line into the L1 cache when cached lines are reused within a certain time period or accessed sequentially.

Enable or disable L2 Stream HW Prefetcher.

Fetch the next cache line into the L2 cache when cached lines are reused within a certain time period or accessed sequentially.

Enable or disable L1 Stride Prefetcher.

Use memory access history to fetch additional data lines into L1 cache when each access is at a constant distance from the previous one. Some workloads may benefit when this feature is set to [Disabled].

Enable or disable L1 Region Prefetcher.

Fetch additional data lines into L1 cache when the data access for a given instruction tends to be followed by a consistent pattern of subsequent accesses. Some workloads may benefit when this feature is set to [Disabled].

Enable or disable L2 Up/Down Prefetcher.

Use memory access history to determine to fetch the next or previous line for all memory accesses. Some workloads may benefit when this feature is set to [Disabled].

This feature can be used to disable symmetric multithreading. To re-enable SMT, a power cycle is needed after selecting [Enabled].

CPPC (cooperative processor performance control) is a way for the operating system to affect the performance of a processor on a contiguous and abstract scale without knowledge of power budgets or discrete processor frequencies.

Maximum boost frequency.

[Auto] sets the boost frequency to the fused value for the installed processor.

When a manual value is entered, the value entered is a 4 digit number representing the maximum boost frequency in MHz. The value entered applies to all cores.

Maximum boost frequency.

Enable or disable processor Virtualization.

Sets the xGMI maximum allowable link width. The actual xGMI link width can vary between the minimum and maximum width selected.

[Auto]: Set the maximum xGMI link width based on the system capabilities.

[xAPIC] scales to only 255 hardware threads.

[x2APIC] scales beyond 255 hardware threads but not supported by some legacy OS versions.

[Auto] uses [x2APIC] only if 256 hardware threads are in the system. Otherwise, use [xAPIC].

Enable the support for Secure Encrypted Virtualization and Secure Nested Paging.

HSMP (Host System Management Port) is an interface to provide OS-level software with access to system management functions via a set of mailbox registers

• [Auto]: Use hardware default value.

• [Enabled]: Enable HSMP interface support.

• [Disabled]: Disable HSMP interface support.

(ERSM) Can be disabled for analysis purposes as long as OS supports it.

(FSRM) Can be disabled for analysis purposes as long as OS supports it.

[Enabled] means that the ENTIRE system memory is covered.

3D V-Cache only takes effect in systems powered by AMD EPYC Processors equipped with AMD 3D V-Cache technology. Lenovo recommends setting this option to [Auto] to leverage the extra cache. If your application is not cache or memory bandwidth sensitive, then Lenovo recommends setting this option to [Disabled].

Enter in microseconds (decimal value).

Larger C2 latency values will reduce the number of C2 transitions and reduce C2 residency. Fewer transitions can help when performance is sensitive to the latency of C2 entry and exit. Higher residency can improve performance by allowing higher frequency boost and reduce idle power. The best value will be dependent on kernel version, use case, and workload.

Select total number of enabled CPU cores per socket to be activated. Available options are dependent on processor SKU topology.

Secured-Core configuration setup page.