Operating Modes
Select the operating mode based on your preference.
| Item | Options | Description |
|---|---|---|
| Choose Operating Mode |
| Select the operating mode based on your preference. Power savings and performance are also highly dependent on hardware and software running on the system. |
| Determinisim Slider |
| When set to [Performance], performance is more predictable (deterministic) and operates at the lowest common denominator among the cores. But aggregate peak performance may be reduced. When set to [Power], cores can scale frequency independently. Aggregate performance may be higher, but predictability is lower. |
| Core Performance Boost |
| When set to [Enabled], cores can go to turbo frequencies. |
| cTDP |
| Set the maximum power consumption for the processor. [Auto] sets cTDP=TDP for the installed processor SKU. [Maximum] sets the maximum allowed cTDP value for the installed processor SKU. Usually, maximum is greater than TDP. If a manual value is entered that is larger than the max value allowed, the value will be internally limited to the maximum allowable value. cTDP is only configurable before OS boot. |
| cTDP Manual | [0] | Set the maximum power consumption for the processor. [Auto] sets cTDP=TDP for the installed processor SKU. [Maximum] sets the maximum allowed cTDP value for the installed processor SKU. Usually, maximum is greater than TDP. If a manual value is entered that is larger than the max value allowed, the value will be internally limited to the maximum allowable value. cTDP is only configurable before OS boot. |
| Package Power Limit |
| Sets the processor package power limit. If [Auto] is selected, it will be set to the maximum value allowed by the installed processor. If a manual value is entered that is larger than the maximum value allowed, the value will be internally limited to the maximum allowable value. The maximum value allowed for PPL is the cTDP limit. Compared to cTDP, PPL can also be changed at runtime and PPL supports a much lower effective limit than cTDP. |
| Package Power Limit Manual | [0] | Package Power Limit (PPT) [W]. |
| Memory Speed |
| The option number of the memory speed is changed dynamically according to the combination of the installed processor SKU, DIMM type, number of DIMMs per channel, and system board support. The system operates at the rated speed of the slowest DIMM in the system when populated with different speed DIMMs. If DIMMs are installed with a rated speed below 3600, this will result in the memory speed getting set to the Minimum value. |
| Efficiency Mode |
| Enables/disables efficiency mode. When enabled, uses power efficiency optimized CCLK DPM settings. |
| Global C-state Control |
| Global enables/disable for IO based C-state generation and DF C-states. |
| DF P-states |
| When [Auto] is selected, the processor DF P-states (uncore P-states) will be dynamically adjusted. That is, their frequency will dynamically change based on the workload. Selecting P0, P1, P2, P3 or P4 forces the DF to a specific P-state frequency. |
| DF C-States |
| Enables/disable data fabric (DF) C-states. Data fabric C-states may be entered when all cores are in CC6. |
| MONITOR/MWAIT |
| MONITOR/MWAIT instructions are used to engage C-states. Some operating systems will re-enable C-states even when they are disabled in CMOS. To prevent this:
|
| P-state 1 |
| Enable/disable processor P1 P-state. |
| P-State 2 |
| Enable/disable processor P2 P-state. |
| Memory Power Down Enable |
| Enable/disable low-power features for DIMMs. |
| NUMA Nodes per Socket |
| Specify the number of desired NUMA nodes per processor socket (e.g. NPS1 means 1 NUMA per socket). NPS0 will attempt to interleave the 2 processor sockets together (non-NUMA mode). |
| L1 Stream HW Prefetcher |
| Enable/disable L1 stream HW prefetcher. Fetches the next cache line into the L1 cache when cached lines are reused within a certain time period or accessed sequentially. |
| L2 Stream HW Prefetcher |
| Enable/disable L2 stream HW prefetcher. Fetches the next cache line into the L2 cache when cached lines are reused within a certain time period or accessed sequentially. |
| SMT Mode |
| Can be used to disable symmetric multithreading. To re-enable SMT, a power cycle is needed after selecting Enable. |
| Memory Interleave |
| Enable or disable memory interleaving. Note that the NUMA nodes per socket value will be honored regardless of this setting. |
| Chipselect Interleaving |
| This setting specifies if the system should use a DRAM rank also known as chipselect interleaving. This feature will spread memory accesses across the banks of memory within a channel and will increase memory block access performance. This setting requires that the populated DIMMs have the same bank size, type, and that the number of banks is a power of two. It is strongly recommended that DIMMs with the same part number be populated. |
| ACPI SRAT L3 Cache as NUMA Domain |
| When enabled, each CCX in the system will be declared as a separate NUMA domain. When disabled, memory addressing/NUMA nodes per socket will be declared. |
| Acoustic mode |
| Acoustic modes reduce system acoustics by limiting fan speeds. Mode 2 attempts to reduce acoustics more aggressively than Mode 1. When the acoustic mode is set to Disabled, no system fan speed limits are applied. Throttling may momentarily occur when the acoustic mode is set to Mode 1 or Mode 2. To maintain system operation during fan failures, high ambient temperatures or component over temperature conditions, acoustic mode fan limits will be overridden to ensure adequate system airflow. For the high ambient temperature threshold for a specific system, refer to the system documentation. |