Processors

When set to [Performance], performance is more predictable (deterministic) and operates at the lowest common denominator among the cores. But aggregate peak performance may be reduced.

When set to [Power], cores can scale frequency independently. Aggregate performance may be higher, but predictability is lower.

When set to [Enable], cores can go to turbo frequencies.

Set the maximum power consumption for the processor.

[Auto] sets cTDP=TDP for the installed processor SKU.

[Maximum] sets the maximum allowed cTDP value for the installed processor SKU. Usually, maximum is greater than TDP. If a manual value is entered that is larger than the max value allowed, the value will be internally limited to the maximum allowable value.

cTDP is only configurable before OS boot.

Set the maximum power consumption for the processor.

[Auto] sets cTDP=TDP for the installed processor SKU.

[Maximum] sets the maximum allowed cTDP value for the installed processor SKU. Usually, maximum is greater than TDP. If a manual value is entered that is larger than the max value allowed, the value will be internally limited to the maximum allowable value. cTDP is only configurable before OS boot.

Set the processor package power limit.

If [Auto] is selected, it will be set to the maximum value allowed by the installed processor.

If a manual value is entered that is larger than the maximum value allowed, the value will be internally limited to the maximum allowable value.

The maximum value allowed for PPL is the cTDP limit. Compared to cTDP, PPL can also be changed at runtime and PPL supports a much lower effective limit than cTDP.

Package Power Limit (PPT) [W].

Global enables/disable for IO based C-state generation and DF C-states.

When [Auto] is selected, the processor DF P-states (uncore P-states) will be dynamically adjusted. That is, their frequency will dynamically change based on the workload.

Selecting P0, P1, P2, P3 or P4 forces the DF to a specific P-state frequency.

Enable/disable data fabric (DF) C-states.

Data fabric C-states may be entered when all cores are in CC6.

Enable/disable processor P1 P-state.

Enable/disable processor P2 P-state.

When [Enabled], each CCX in the system will be declared as a separate NUMA domain.

When [Disabled], memory addressing/NUMA nodes per socket will be declared.

Enable/disable L1 stream HW prefetcher.

Fetch the next cache line into the L1 cache when cached lines are reused within a certain time period or accessed sequentially.

Enable/disable L2 Stream HW Prefetcher.

Fetch the next cache line into the L2 cache when cached lines are reused within a certain time period or accessed sequentially.

Enable/disable L1 Stride Prefetcher.

Use memory access history to fetch additional data lines into L1 cache when each access is a constant distance from the previous. Some workloads may benefit from having it [Disabled].

Enable/disable L1 Region Prefetcher.

Fetch additional data lines into L1 cache when the data access for a given instruction tends to be followed by a consistent pattern of subsequent accesses. Some workloads may benefit from having it [Disabled].

Enable or disable L2 Up/Down Prefetcher.

Uses memory access history to determine whether to fetch the next or previous line for all memory accesses. Some workloads may benefit from having it [Disabled].

Can be used to disable symmetric multithreading. To re-enable SMT, a power cycle is needed after selecting [Enabled].

CPPC (cooperative processor performance control) is a way for the OS to influence the performance of a CPU on a contiguous and abstract scale without knowledge of power budgets or discrete processor frequencies.

Maximum boost frequency.

[Auto] set the boost frequency to the fused value for the installed processor.

When a manual value is entered, the value entered is a 4 digit number representing the maximum boost frequency in MHZ. The value entered applies to all cores.

Maximum boost frequency.

[Auto] set the boost frequency to the fused value for the installed processor.

When a manual value is entered, the value entered is a 4 digit number representing the maximum boost frequency in MHZ. The value entered applies to all cores.

Enable/disable processor Virtualization.

APIC Mode.

[xAPIC] scales to only 255 hardware threads.

[x2APIC] scales beyond 255 hardware threads but is not supported by some legacy OS versions.

[Auto] uses [x2APIC] only if 256 hardware threads are in the system. Otherwise xAPIC is used.

Enable the support for Secure Encrypted Virtualization and Secure Nested Paging.

Select HSMP support enable or disable.

(ERSM) Can be disabled for analysis purposes as long as OS supports it.

Select the total number of enabled CPU cores per socket to be activated. Options available are dependent on CPU SKU topology.

Secured-Core configuration setup page.