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DCPMM Installation order: Mixed Memory mode with eight processors

When implementing Mixed Memory mode, any supported DIMMs in any capacity can be installed.

When eight processors are installed in the server:

  • Processors 1 and 2 are installed in the lower system board of the lower compute tray.

  • Processors 3 and 4 are installed in the upper system board of the lower compute tray.

  • Processors 5 and 6 are installed in the lower system board of the upper compute tray.

  • Processors 7 and 8 are installed in the upper system board of the upper compute tray.

Several configurations are supported with implementing Mixed Memory mode with eight processors:

  • 6 DCPMMs/ 6 DRAM DIMMs per processor

  • 4 DCPMMs/ 6 DRAM DIMMs per processor

  • 2 DCPMMs/ 6 DRAM DIMMs per processor

  • 2 DCPMMs/ 4 DRAM DIMMs per processor

6 DCPMMs/ 6 DRAM DIMMs per processor​

Table 1. Mixed Memory mode with 6 DCPMMs and 6 DRAM DIMMs per processor (8 processors).
In the table below:

  • P = DCPMM

  • D = DRAM DIMM

Processor 1Processor 2
123456 789101112131415161718 192021222324
DPDPDP PDPDPDDPDPDP PDPDPD
Processor 3Processor 4
123456 789101112131415161718 192021222324
DPDPDP PDPDPDDPDPDP PDPDPD
Processor 5Processor 6
123456 789101112131415161718 192021222324
DPDPDP PDPDPDDPDPDP PDPDPD
Processor 7Processor 8
123456 789101112131415161718 192021222324
DPDPDP PDPDPDDPDPDP PDPDPD

4 DCPMMs/ 6 DRAM DIMMs per processor​

Table 2. Mixed Memory mode with 4 DCPMMs and 6 DRAM DIMMs per processor (8 processors).
In the table below:

  • P = DCPMM

  • D = DRAM DIMM

Processor 1Processor 2
123456 789101112131415161718 192021222324
D DPDP PDPD DD DPDP PDPD D
Processor 3Processor 4
123456 789101112131415161718 192021222324
D DPDP PDPD DD DPDP PDPD D
Processor 5Processor 6
123456 789101112131415161718 192021222324
D DPDP PDPD DD DPDP PDPD D
Processor 7Processor 8
123456 789101112131415161718 192021222324
D DPDP PDPD DD DPDP PDPD D

2 DCPMMs/ 6 DRAM DIMMs per processor​

Note
Only RDIMMs are recommended for this configuration
Table 3. Mixed Memory mode with 2 DCPMMs and 6 DRAM DIMMs per processor (8 processors).
In the table below:

  • P = DCPMM

  • D = DRAM DIMM

Processor 1Processor 2
123456 789101112131415161718 192021222324
D D DP PD D DD D DP PD D D
Processor 3Processor 4
123456 789101112131415161718 192021222324
D D DP PD D DD D DP PD D D
Processor 5Processor 6
123456 789101112131415161718 192021222324
D D DP PD D DD D DP PD D D
Processor 7Processor 8
123456 789101112131415161718 192021222324
D D DP PD D DD D DP PD D D

2 DCPMMs/ 4 DRAM DIMMs per processor​

Table 4. Mixed Memory mode with 2 DCPMMs and 4 DRAM DIMMs per processor (8 processors).
In the table below:

  • P = DCPMM

  • D = DRAM DIMM

Processor 1Processor 2
123456 789101112131415161718 192021222324
P D D   D D PP D D   D D P
Processor 3Processor 4
123456 789101112131415161718 192021222324
P D D   D D PP D D   D D P
Processor 5Processor 6
123456 789101112131415161718 192021222324
P D D   D D PP D D   D D P
Processor 7Processor 8
123456 789101112131415161718 192021222324
P D D   D D PP D D   D D P