Processors

Summary of the installed processors

Enabling Turbo mode can boost the overall CPU performance when all CPU cores are not being fully utilized. A CPU core can run above its rated frequency for a short period of time when it is in Turbo mode.

When energy efficient turbo is enabled, the CPU's optimal turbo frequency will be tuned dynamically based on CPU utilization. The Power/Performance Bias setting also influences energy efficient Turbo.

Enable or disable Turbo Boost Max 3.0.

Intel^® Turbo Boost Max Technology 3.0 is an enhanced version of 2.0 that boosts the speed of a CPU’s fastest cores individually, while also directing critical workloads to those boosted cores.

The processor active power management state (P-state control) affects how the CPU operating frequencies are selected, based on the workload.

• [Autonomous]: This mode is part of Intel’s Hardware Power Management (HWPM) feature and is the default mode. In this mode, all CPU P-state management is handled automatically in the background without any OS intervention. Autonomous mode is used for normal power savings and serves well for most typical business applications.

• [Legacy]: The processor P-states will be presented to the OS and the OS power management (OSPM) will directly control which P-state is selected. Legacy control mechanism is currently implemented for systems with processors prior to the Intel Xeon Scalable Processor codenamed Skylake. Uses the standard ACPI interface. This mode is used for applications which benefit from OS level frequency controls.

• [Cooperative without Legacy]: UEFI doesn't provide legacy P-States. The OS provides hints to the processor's power control unit (PCU) for the desired P-state min/max levels. The PCU runs in Autonomous mode until the OS sets the desired frequency. The hints provided by the OS affect the final P-state selected by the PCU.

• [Cooperative with Legacy]: UEFI leaves the legacy P-states interface initially enabled until/if later an OS that is aware of Intel Hardware P-states (HWP) native mode sets the bit. Legacy P-states will be used until the OS sets the HWP native mode. After that, P-states will switch to the same behavior as "Cooperative without Legacy".

• [None]: No ACPI table entries for P-states are created. P-states are disabled. Use this setting to minimize latency caused by P-state transitions. Recommended for latency sensitive workloads. CPUs run at either their rated frequency or in turbo mode, if turbo is enabled.

For applications which are clock frequency sensitive it is recommended to test with Cooperative or Legacy mode.

C-states reduces power consumption during the idle time.

When [Legacy] is selected, the operating system initiates the C-state transitions. Some OS software may defeat the ACPI mapping (e.g. intel_idle driver).

Low power C-states have higher exit latencies and higher power C-states have lower exit latencies.

Enabling C1E (C1 enhanced) state can save power by halting CPU cores that are idle. An operating system that supports C1E state must be installed to support this feature.

When enabled, the processor will dynamically change frequencies based on the workload. All miscellaneous logic inside the CPU package is considered the Uncore.

Enable or disable Intel Trusted Execution Technology (Intel TXT).

Intel TXT is a set of hardware extensions to Intel processors and chipsets that enhance the digital office platform with security capabilities such as measured launch and protected execution.

Enable or disable Intel Virtualization Technology.

Intel Virtualization Technology abstracts hardware that allows multiple workloads to share a common set of resources.

When enabled, the hardware prefetcher will prefectch data from the main system memory to the Level 2 cache to help expedite data transaction for memory performance enhancement.

Lightly-threaded applications and some benchmarks can benefit from having the hardware prefetcher enabled.

The adjacent cache line prefetcher automatically fetches adjacent cache lines to ones being accessed by the program. This reduces cache latency by making the next cache line immediately available if the processor requires it.

Lightly-threaded applications and some benchmarks can benefit from having Adjacent Cache Prefetch enabled.

The Data Cache Unit (DCU) streamer prefetcher detects multiple reads to a single cache line in a certain period of time and choose to load the following cache line to the L1 data caches.

Lightly-threaded applications and some benchmarks can benefit from having DCU Streamer Prefetcher enabled.

DCU IP prefetcher looks for sequential load history to determine whether to prefetch the following data to the L1 caches.

It is recommended that the DCU IP prefetcher is enabled for the most environments. However, some environments may benefit from having it disabled, e.g. Java.

Next page prefetcher is an L1 data cache page prefetcher (MSR 1A4h [4]), which detects accesses that are likely to cross a page boundary and starts the access early.

Limiting the QPI/UPI connections to the minimum number can save power. If maximum performance is desired, all QPI links should be left enabled.

Sub NUMA Clustering (SNC) partitions the cores and last level cache (LLC) into clusters with each cluster bound to a set of memory controllers in the system, dividing each CPU package into multiple NUMA nodes. This can improve average latency to the last level cache.

When enabled, additional features such as Opportunistic Snoop Broadcast (OSB), HitME cache, and I/O Directory Cache (IODC) are used to reduce the overhead of directory reads. When disabled, all memory accesses will require a snoop which is not recommended for most workloads.

Extended Prediction Table (XPT) prefetcher (memory prefetch from the core) is a mechanism that enables a read request that is being sent to the last level cache to speculatively issue a copy of that read to the memory controller prefetching. It is designed to reduce local memory access latency.

Ultra Path Interconnect (UPI) prefetch enables an early memory read on the memory bus. The UPI receive path spawns a memory read to the memory controller prefetcher.

Latency saving feature for remote read transactions. Workloads that are highly dependent on remote idle latency may see an impact when D2U is disabled.

When I/O Directory Cache (IODC) is enabled, this reduces directory-based write overhead. When disabled, it does not suppress directory read/updates for non-cacheable write transactions.

The BIOS option provides a set of thresholds that can control how much of the various types of requests are allowed to occupy the Table Of Requests (TOR), thus helping to avoid the imbalance between local requests and remote requests. This BIOS option controls the number of local-to-remote (Loctorem) requests allowed in the pipeline when the pipeline is empty of remote requests (EMPTY) and when remote requests are also present in the pipeline (NORMAL).

Auto is default and controlled by Si Compatibility.

The BIOS option provides a set of thresholds that can control how much of the various types of requests are allowed to occupy the Table Of Requests (TOR), thus helping to avoid the imbalance between local requests and remote requests. This BIOS option controls the number of local-to-remote (Loctorem) requests allowed in the pipeline when the pipeline is empty of remote requests (EMPTY) and when remote requests are also present in the pipeline (NORMAL).

Auto is default and controlled by Si Compatibility.

Intel Total Memory Encryption (TME) encrypts the entire physical memory of a system with a single encryption key.

Intel Multikey Total Memory Encryption (MK-TME) technology is built on top of Intel TME. It enables the use of multiple encryption keys, allowing selection of one encryption key per memory page using the processor page tables.

Enable or disable memory integrity. Memory integrity is a feature of core isolation.

Total number of keys that can be used by TME-MT.

Enable or disable Trust Domain Extension (TDX).

Designate number of bits for TDX usage. The rest will be used by TME-MT.

Enable or disable Software Guard Extensions (SGX).

Enable or disable SGX Factory Reset.

When [Enabled] is selected, it erases all registration data on subsequent boot, and additionally forces an Initial Platform Establishment flow when SGX is enabled.

Enable or disable Software Guard Extensions (SGX) Package Info In-Band Access.

SGX PRM Size is a constituent which may not be equal to the total PRM size.

With Intel Speed Select Technology (SST), the rated frequency of the CPU can increase as the number of CPU cores that are enabled in UEFI goes down. Essentially, with SST, the CPU can achieve a guaranteed turbo frequency.

If the processor installed doesn't support SST, the [Base] option will be used regardless of the setting selected.

• [Bases]: effectively disables SST.

• [Auto]: The level of SST enablement is controlled automatically based on the number of CPU cores enabled in UEFI.

• [Config1]: forces the SST cores limits based on the Config option selected. [Config1] may override the option that enables the number CPU cores in UEFI.

• [Config2]: forces the SST cores limits based on the Config option selected. [Config2] may override the option that enables the number CPU cores in UEFI.

• [SST-PP V2] enables dynamic SST-PP mode. With SST-PP V2, the mode can be dynamically changed at runtime via the Linux OS.

This Option allows SST-BF to be enabled and allows BIOS to configure SST-BF High Priority Cores so that software does not have to configure it.

Enable or disable trust for the Platform Environment Control Interface (PECI) of the system.

You can select [Disabled] if a higher level of security is required, but some functions such as memory and I/O utilization reporting may not work.

Select the amount of cores enabled within each CPU package.

Enabling CPU PCIe Relaxed Ordering will always allow downstream completions to pass posted writes.

The Opportunistic Snoop Broadcast(OSB) feature attempts to avoid memory read latency by snooping the local (home) agent and remote socket peers.

Auto is default and controlled by Si Compatibility.

Auto is default and controlled by Si Compatibility.

Auto is default and controlled by Si Compatibility.

Auto is default and controlled by Si Compatibility.

When OSB indicates that there aren't enough snoop credits, no IODC entry will be allocated.

Auto is default and controlled by Si Compatibility.

State AtoS controls whether a cache line should transition from A (snoopAll) state to S (Shared) state when snoop misses.

• [Enabled]: The LLC opportunistically fills dead lines into LLC if there is free space available.

• [Disabled]: Dead lines will always be dropped and will never fill into the LLC.

Select the desired UPI link frequency.

• [Maximum performance]: maximizes the performance.

• [Balanced]: offers a balance between performance and power.

• [Minimal power]: maximizes power savings.

The maximum frequency (turbo, AVX, and non turbo) can be restricted to a frequency that is between the maximum turbo frequency for the CPU installed and 1.2 GHz. This can be useful for synchronizing CPU tasks.

The max frequency for N+1 cores cannot be higher than N cores. If an unsupported frequency is entered, it will automatically be limited to a supported value. If the CPU frequency limits are being controlled through application software, leave this menu item at the default setting ([Full turbo uplift]).

When [Enabled] is selected, Rocket Mode allows the cores to jump to max turbo instantly rather than on a smooth curve.

When Rocket Mode is enabled, it is only engaged when P-states are set to [Autonomous].

Controls maximum allowed time to nap in C0 sub-state, and to control whether C0.2 is supported.